Technical Field
This application relates to integrated circuit (IC) packages and wafer scale methods for making them in general, and in particular, to making two-dimensional (2D) and three-dimensional (3D) IC packages using integrated interposers (ITPs).
Related Art
In recent years, the size of semiconductor chips has shrunk dramatically in order to achieve a number of performance goals, e.g., higher signal propagation, lower power consumption, lower fabrication costs, and reduced form factors, among others. As the semiconductor industry has struggled to pack more functionality into smaller and smaller spaces, some have suggested that, without new ground-breaking technologies in processing and assembly, the well-known “Moore's law,” i.e., that the number of transistors in densely integrated circuits doubles approximately every two years over the history of computing hardware, may cease to hold true. Vertical integration, i.e., three-dimensional integrated circuit (“3D IC” or “3D”) packaging, has emerged as one of the more promising technology to achieve the above goals.
However, 3D IC packaging presents designers and fabricators with a number of challenges. For example, a current trend in 3D IC assembly is to assemble microbumped dies onto thin interposers (ITPs). However, fabrication and assembly of relatively thin ITPs can create a number of problems. One is that, in order to thin the ITP down to the desired thickness, the ITP wafer is typically mounted on a “carrier” with temporary adhesives, typically low-melting-temperature polymers, during the thinning and subsequent processing. The relatively low melting temperatures of the adhesives limit the overall maximum temperatures that can be used in so-called “backside” processing. Wafer breakage is also increased during the demounting process and associated wafer handling. Another problem is a warpage issue that can occur during assembly in that, not only it is it very difficult to connect microbumps to a warped ITP die, but the warpage also creates a long term reliability issue by imposing stresses on solder bumps and functional dies.
Accordingly, a long felt but as yet unsatisfied need exists for 2D and 3D IC designs and manufacturing methods that overcome the foregoing and other problems of the prior art.